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DG406, DG407
Data Sheet March 13, 2006 FN3116.9
Single 16-Channel/Differential 8-Channel, CMOS Analog Multiplexers
The DG406 and DG407 monolithic CMOS analog multiplexers are drop-in replacements for the popular DG506A and DG507A series devices. They each include an array of sixteen analog switches, a TTL and CMOS compatible digital decode circuit for channel selection, a voltage reference for logic thresholds, and an ENABLE input for device selection when several multiplexers are present. These multiplexers feature lower signal ON resistance (<100) and faster transition time (tTRANS < 300ns) compared to the DG506A and DG507A. Charge injection has been reduced, simplifying sample and hold applications. The improvements in the DG406 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 30VP-P signals when operating with 15V power supplies. The sixteen switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a 5V analog input range.
Features
* ON-Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . 100 * Low Power Consumption (PD) . . . . . . . . . . . . . . . <1.2mW * Fast Transition Time (Max) . . . . . . . . . . . . . . . . . . . . 300ns * Low Charge Injection * TTL, CMOS Compatible * Single or Split Supply Operation * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Battery Operated Systems * Data Acquisition * Medical Instrumentation * Hi-Rel Systems * Communication Systems * Automatic Test Equipment
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
Pinouts
DG406 (PDIP, SOIC) TOP VIEW
V+ 1 NC 2 NC 3 S16 4 S15 5 S14 6 S13 7 S12 8 S11 9 S10 10 S9 11 GND 12 NC 13 A3 14 28 D 27 V26 S8 25 S7 24 S6 23 S5 22 S4 21 S3 20 S2 19 S1 18 EN 17 A0 16 A1 15 A2
DG407 (PDIP, SOIC) TOP VIEW
V+ 1 DB 2 NC 3 S8B 4 S7B 5 S6B 6 S5B 7 S4B 8 S3B 9 S2B 10 S1B 11 GND 12 NC 13 NC 14 28 DA 27 V26 S8A 25 S7A 24 S6A 23 S5A 22 S4A 21 S3A 20 S2A 19 S1A 18 EN 17 A0 16 A1 15 A2
Ordering Information
PART NUMBER DG406DJ DG406DJZ (See Note) DG406DY DG406DY-T DG406DYZ (See Note) DG406DYZ-T (See Note) DG407DJ DG407DJZ (Note) DG407DY DG407DYZ (Note) PART MARKING DG406DJ DG406DJZ DG406DY DG406DY DG406DYZ DG406DYZ DG407DJ DG407DJZ DG407DY DG407DYZ TEMP. RANGE (C) PACKAGE -40 to 85 -40 to 85 -40 to 85 28 Ld PDIP PKG. DWG. # E28.6
28 Ld PDIP* E28.6 (Pb-free) 28 Ld SOIC M28.3
28 Ld SOIC Tape and Reel M28.3 -40 to 85 28 Ld SOIC (Pb-free) M28.3
28 Ld SOIC Tape and Reel M28.3 (Pb-free) -40 to 85 -40 to 85 -40 to 85 -40 to 85 28 Ld PDIP E28.6
28 Ld PDIP* E28.6 (Pb-free) 28 Ld SOIC 28 Ld SOIC (Pb-free) M28.3 M28.3
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2000, 2003, 2004, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
DG406, DG407 Schematic Diagram (Typical Channel)
V+ GND VREF D A0 V+ AX LEVEL SHIFT DECODE/ DRIVE V-
S1
V+ EN SN V-
Functional Diagrams
DG406
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 TO DECODER LOGIC CONTROLLING BOTH TIERS OF MUXING ADDRESS DECODER 1 OF 16 D S1B S2B S3B S4B S5B S6B S7B S8B TO DECODER LOGIC CONTROLLING BOTH TIERS OF MUXING ENABLE ADDRESS DECODER 1 OF 8 DB S1A S2A S3A S4A S5A S6A S7A S8A DA
DG407
ENABLE
A0
A1
A2
A3
EN
A0
A1
A2
EN
2
FN3116.9 March 13, 2006
DG406, DG407
DG406 TRUTH TABLE A3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ON SWITCH None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 DG407 TRUTH TABLE A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 ON SWITCH PAIR None 1 2 3 4 5 6 7 8
Logic "0" = VAL < 0.8V. Logic "1" = VAH > 2.4V. X = Don't Care.
3
FN3116.9 March 13, 2006
DG406, DG407
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Digital Inputs, VS , VD (Note 1). . . . . . (V-) -2V to (V+) +2V or 20mA, Whichever Occurs First Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 100mA
Thermal Information
Thermal Resistance (Typical, Note1)
JA (oC/W)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (PLCC and SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. Signals on SX , DX , EN or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.
Electrical Specifications
PARAMETER DYNAMIC CHARACTERISTICS Transition Time, tTRANS
Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V Unless Otherwise Specified TEST CONDITIONS TEMP (oC) (NOTE 3) MIN (NOTE 4) TYP (NOTE 3) MAX UNITS
(See Figure 1)
25 Full
25 10 -
200 50 150 70 40 -69 7 8
300 400 200 400 150 300 -
ns ns ns ns ns ns ns ns pC dB pF pF
Break-Before-Make Interval, tOPEN Enable Turn-ON Time, tON(EN) Enable Turn-OFF Time, tOFF(EN) Charge Injection, Q OFF Isolation, OIRR Logic Input Capacitance, CIN Source OFF Capacitance, CS(OFF) Drain OFF Capacitance, CD(OFF) DG406 DG407 Drain ON Capacitance, CD(ON) DG406 DG407 DIGITAL INPUT CHARACTERISTICS Logic High Input Voltage, VINH Logic Low Input Voltage, VINL Logic High Input Current, IAH Logic Low Input Current, IAL ANALOG SWITCH CHARACTERISTICS Drain-Source ON Resistance, rDS(ON) rDS(ON) Matching Between Channels, rDS(ON)
(See Figure 3)
25 Full
(See Figure 2)
25 Full 25 Full
CL = 1nF, VS = 0V, RS = 0 VEN = 0V, RL = 1k, f = 100kHz (Note 7) f = 1MHz VEN = 0V, VS = 0V, f = 1MHz VEN = 0V, VD = 0V, f = 1MHz
25 25 25 25
25 25
-
160 80 180 90
-
pF pF pF pF
VEN = 5V, VD = 0V, f = 1MHz
25 25
Full Full VA = 2.4V, 15V VEN = 0V, 2.4V, VA = 0V VD = 10V, IS = +10mA (Note 5) VD = 10V, -10V (Note 6) Full Full
2.4 -1 -1
-
0.8 1 1
V V A A %
25 Full 25
-
50 5
100 125 -
4
FN3116.9 March 13, 2006
DG406, DG407
Electrical Specifications
PARAMETER Source OFF Leakage Current, IS(OFF) Drain OFF Leakage Current, ID(OFF) DG406 25 Full DG407 VS = VD = 10V (Note 5) 25 Full DG407 25 Full POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ VEN = VA = 0V or 5V (Standby) 25 Full 25 Full Positive Supply Current, I+ VEN = 2.4V, VA = 0V (Enabled) 25 Full 25 Full -1 -10 -1 -10 13 -0.01 80 -0.01 30 75 100 200 A A A A A A A A -1 -40 -1 -20 0.04 0.04 1 40 1 20 nA nA nA nA 25 Full Drain ON Leakage Current, ID(ON) DG406 -1 -40 -1 -20 0.04 0.04 1 40 1 20 nA nA nA nA Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V Unless Otherwise Specified TEST CONDITIONS VEN = 0V, VS = 10V, VD = +10V TEMP (oC) 25 Full (NOTE 3) MIN -0.5 -5 (NOTE 4) TYP 0.01 (Continued) (NOTE 3) MAX 0.5 5 UNITS nA nA
Negative Supply Current, I-
Negative Supply Current, I-
Electrical Specifications
Single Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified TEST CONDITIONS TEMP (oC) (NOTE 3) MIN (NOTE 4) TYP (NOTE 3) MAX UNITS
PARAMETER DYNAMIC CHARACTERISTICS Switching Time of Multiplexer, tTRANS Enable Turn-ON Time, tON(EN) Enable Turn-OFF Time, tOFF(EN) Charge Injection, Q
VS1 = 8V, VS8 = 0V, VIN = 2.4V VINH = 2.4V, VINL = 0V, VS1 = 5V
25 25 25 25
-
300 250 150 20
450 600 300 -
ns ns ns pC
CL = 1nF, VS = 6V, RS = 0
5
FN3116.9 March 13, 2006
DG406, DG407
Electrical Specifications
Single Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) (NOTE 3) MIN (NOTE 4) TYP (NOTE 3) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON-Resistance, rDS(ON) rDS(ON) Matching Between Channels (Note 6), rDS(ON) Source Off Leakage Current, IS(OFF) Drain Off Leakage Current, ID(OFF) DG406 DG407 Drain On Leakage Current, ID(ON) DG406 DG407 POWER SUPPLY CHARACTERISTICS Positive Supply Current (I+) (Standby) Negative Supply Current (I-) (Enabled) NOTES:
Full VD = 3V, 10V, IS = -1mA (Note 5) 25 25 VEN = 0V, VD = 10V or 0.5V, VS = 0.5V or 10V 25
0 -
90 5 0.01
12 120 -
V % nA
25 25 VS = VD = 10V (Note 5) 25 25
-
0.04 0.04
-
nA nA
-
0.04 0.04
-
nA nA
VEN = 0V or 5V, VA = 0V or 5V
25 Full 25 Full
-1 -5
13 13 -0.01 -0.01
30 75 -
A A A A
3. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 4. Typical values are for Design Aid Only, not guaranteed nor production tested. 5. Sequence each switch ON. 6. rDS(ON) = (rDS(ON)(Max) - rDS(ON)(Min)) / rDS(ON) average. 7. Worst case isolation occurs on channel 8B due to proximity to the drain pin.
Test Circuits and Waveforms
+15V +15V V+
+2.4V
EN A3 A2
V+
S1
10V LOGIC INPUT VO 300 35pF
+2.4V
EN A2
S1B S8B DB
10V
S2 - S15 DG406 S 16 VD 10V
LOGIC INPUT 50
A1
A1 A0 GND
A0 GND 50
V-
300 -15V = S1A - S8A , S2B - S7B , DA
-15V
FIGURE 1A. DG406 TEST CIRCUIT
FIGURE 1B. DG407 TEST CIRCUIT
6
DG407
10V VO 35pF
FN3116.9 March 13, 2006
DG406, DG407 Test Circuits and Waveforms
(Continued)
tr < 20ns tf < 20ns 50% 0V VS1B SWITCH OUTPUT VO 0V 80% VS8B tTRANS S8 ON tTRANS VS8 S1 ON 80% VS1 50%
LOGIC INPUT
3V
FIGURE 1C. MEASUREMENT POINTS FIGURE 1. TRANSITION TIME
+15V
+15V
A3 A2 LOGIC INPUT VIN 50 A1
V+
S1
-5V LOGIC INPUT VIN VO 300 35pF 50
A2 A1 A0 EN
V+ DG407
S1B
-5V
S2 - S16 DG406 VD
A0 EN GND
DA AND DB GND V300 -15V 35pF
VO
-15V
= S1A - S8A , S2B - S8B , DA
FIGURE 2A. DG406 TEST CIRCUIT
FIGURE 2B. DG407 TEST CIRCUIT
tr < 20ns tf < 20ns 50% 50%
LOGIC INPUT VIN
3V 0V tON(EN) 0V
tOFF(EN)
SWITCH OUTPUT VO VO
90% VO
FIGURE 2C. MEASUREMENT POINTS FIGURE 2. ENABLE SWITCHING TIMES
+15V 3V V+ LOGIC INPUT +5V (VS) 0V VS
tr < 20ns tf < 20ns
+2.4V
EN A3
ALL S AND DA
LOGIC INPUT 50
A2 DG406 DG407 A1 D, A0 GND V- DB 300 -15V 35pF
VO
SWITCH OUTPUT VO
80%
0V tOPEN
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
7
FN3116.9 March 13, 2006
DG406, DG407 Typical Performance Curves
160 rDS(ON) , ON-RESISTANCE () 140 rDS(ON) , ON RESISTANCE () 120 5V 100 80 60 40 20 0 -20 -16 -12 -8 -4 0 4 8 VD , DRAIN VOLTAGE (V) 12 16 20 8V 10V 12V 15V 20V 80 70 60 50 40 30 20 10 0 -15 -40oC -55oC V+ = 15V V- = -15V -10 -5 0 5 10 15 0oC 125oC 85oC 25oC
VD , DRAIN VOLTAGE (V)
FIGURE 4. rDS(ON) vs VD AND SUPPLY
FIGURE 5. rDS(ON) vs VD AND TEMPERATURE
240 rDS(ON) , ON-RESISTANCE () 200 160 10V 120 12V 80 40 0 15V 20V V+ = 7.5V
V- = 0V
120 80 ID , IS , CURRENT (pA) 40 IS(OFF) 0 -40 -80 -120 -15 DG406 ID(ON) , ID(OFF) DG407 ID(ON) , ID(OFF) V+ = 15V, V- = -15V VS = -VD FOR ID(OFF) VD = VS(OPEN) FOR ID(ON)
22V
0
4
8
12
16
20
-10
-5
0
5
10
15
VD , DRAIN VOLTAGE (V)
VS , VD , SOURCE DRAIN VOLTAGE (V)
FIGURE 6. rDS(ON) vs VD AND SUPPLY
FIGURE 7. ID, IS LEAKAGE CURRENTS vs ANALOG VOLTAGE
100nA 10nA ID , IS , CURRENT (A) 1nA
V+ = 15V, V- = -15V VS OR VD = 10V
350 300 250 TIME (ns) 200 tON(EN) 150 100 tOFF(EN) 50 0 tTRANS
100pA 10pA 1pA 0.1pA -55
ID(ON) , ID(OFF)
IS(OFF)
-35
-15
5
25
45
65
85
105
125
5
10
15
20
TEMPERATURE (oC)
VSUPPLY , SUPPLY VOLTAGE (V)
FIGURE 8. ID , IS LEAKAGE vs TEMPERATURE
FIGURE 9. SWITCHING TIMES vs BIPOLAR SUPPLIES
8
FN3116.9 March 13, 2006
DG406, DG407 Typical Performance Curves
700 V- = 0V 600 500 TIME (ns) 400 300 200 tOFF(EN) 100 0 -20 0 100 tTRANS tON(EN) ISOL (dB) -120 -100 -80 -60 -40
(Continued)
-140
5
10
15
20
1K
10K
100K
1M
10M
V+, SUPPLY VOLTAGE (V)
f, FREQUENCY (Hz)
FIGURE 10. SWITCHING TIMES vs SINGLE SUPPLY
FIGURE 11. OFF ISOLATION vs FREQUENCY
10 8 6 I+ I, CURRENT (mA) 4 TIME (ns) 2 0 -2 -4 -6 -8 -10 10 100 1K 10K 100K 1M 10M IIGND EN = 5V, AX = 0V OR 5V
300 280 260 240 220 200 180 160 140 120 100 80 60 -55 -35 -15 5 tOFF(EN) 25 45 65 85 105 125 tON(EN) tTRANS V+ = 15V, V- = -15V
f, FREQUENCY (Hz)
TEMPERATURE (oC)
FIGURE 12. SUPPLY CURRENTS vs SWITCHING FREQUENCY
FIGURE 13. tON /tOFF vs TEMPERATURE
3
2 VA , (V) 1 0 0 5 10 15 20 VSUPPLY, SUPPLY VOLTAGE (V)
FIGURE 14. SWITCHING THRESHOLD vs SUPPLY VOLTAGE
9
FN3116.9 March 13, 2006
DG406, DG407 Die Characteristics
DIE DIMENSIONS: 2490m x 4560m x 485m METALLIZATION: Type: SiAl Thickness: 12kA 1kA PASSIVATION: Type: Nitride Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG406
NC
V+
D
V-
S16
S5
S15
S7
S14
S6
S13
S5
S12
S4
S11
S3
S10
S2
S9
S1
GND A3
A2
A1
A0
EN
10
FN3116.9 March 13, 2006
DG406, DG407 Die Characteristics
DIE DIMENSIONS: 2490m x 4560m x 485m METALLIZATION: Type: SiAl Thickness: 12kA 1kA PASSIVATION: Type: Nitride Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG407
DB V+ DA V-
S8A
S8B
S7A
S7B
S6A
S6B
S5A
S5B
S4A
S4B
S3A
S3B
S2A
S2B
S1A
S1B
GND
NC
A2
A1
A0
EN
11
FN3116.9 March 13, 2006
DG406, DG407 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E28.6 (JEDEC MS-011-AB ISSUE B)
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 1 12/00
MIN 0.015 0.125 0.014 0.030 0.008 1.380 0.005 0.600 0.485
MAX 0.250 0.195 0.022 0.070 0.015 1.565 0.625 0.580
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E E1 e eA eB L N
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.600 BSC 0.115 28 0.700 0.200
2.54 BSC 15.24 BSC 2.93 28 17.78 5.08
12
FN3116.9 March 13, 2006
DG406, DG407 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992
B C D E

A1 0.10(0.004) C
e H h L N
0.05 BSC 0.394 0.01 0.016 28 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 28 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN3116.9 March 13, 2006

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